; Orange programmer module v1.6
; (c) 2006 CnCLab 
; CHIP=93C56 (128x16),93C66 (256x16)
; chips w/o WP 

;AT93C56A,AT93C66,AT93C66A,FM93C66A,NM93C66A

SOCKET=2 ;"MW"
TESTMASK=11110100


PINO=CLK,0
PINO=DI,1
PINO=CS,2
PINO=ORG,3
PINO=NC,4
PINI=DO,1

CDELAY=4 ; one set delay


[!#SETUP]
$WDELAY=10000

[_SEND]
LOOP=(10,0){DI=R0[I],CLK=1,CLK=0}    ; out EWEN


[_WAITWR]
LOOP=(0,10000){
DO?1{BREAK}
P=10
}


[INIT]
NC=1,ORG=1,CS=1,P=10

[READ]
CS=0
CLK=0
CS=1
DI=1,CLK=1,CLK=0    ; start bit
DI=1,CLK=1,CLK=0    ; \ read instruction
DI=0,CLK=1,CLK=0    ; /
LOOP=(7,0){DI=ADR[I],CLK=1,CLK=0}    ; out adr
DI=1,P=1
DO?1{PRINT=A("Chip not respond at %04lX, continue?",ADR),RA?0{EXIT}} 
LOOP=(15,0){CLK=1,CLK=0,DATA[I]=DO}  ; read data word
CS=0

[WRITEINIT]
NC=0
CS=0
CLK=0
CS=1
_SEND(10011000000b)	; out EWEN
CS=0


[WRITE]
CS=0
CLK=0
CS=1
DI=1,CLK=1,CLK=0    ; start bit
DI=0,CLK=1,CLK=0    ; \ write instruction
DI=1,CLK=1,CLK=0    ; /
LOOP=(7,0){DI=ADR[I],CLK=1,CLK=0}    ; out adr
LOOP=(15,0){DI=DATA[I],CLK=1,CLK=0}  ; write data word
CS=0,DI=1,CS=1      ; check status
P=$WDELAY
_WAITWR
DO?1
CS=0

[Erase]
NC=0
CS=0
CLK=0
CS=1

CS=1
_SEND(10011000000b)                   ; out EWEN
CS=0

CS=1
_SEND(10010000000b)                   ; out ERAL
CS=0

P=$WDELAY
P=$WDELAY
_WAITWR

;[END]
;NC=1