; Orange programmer module v2.1
; (c) 1999-2008 CnCLab
; SPI EEPROM:
; CHIP=25c080(1024x8), 25c160 (2048x8) 
; block read/write supported.

SOCKET=4 ;"SPI"

PINO=SCK,0
PINO=SI,1
PINO=CS,2
PINO=WP,3
PINO=HOLD,4
PINI=SO,1

CDELAY=2 ; one set delay

R9=STATUS,C8,WPEN,x,x,x,BL1,BL0,WEL,RDY

[!#SETUP]
$WDELAY=10000

[_SEND]
LOOP=(7,0){SI=R0[I],SCK=P}

[_WAITWR]	;Wait for end write memory...
SCK=0
LOOP=(0,1000){
CS=0
_SEND(00000101b)                ;RDSR
SI=1
R9=0
LOOP=(7,0){SCK=1,R9[I]=SO,SCK=0}
CS=1
R9[0]?0{BREAK}   ;WIP bit
P=10
}


[INIT]
HOLD=1
WP=0
CS=1
SCK=0

_WAITWR       ; READ STATUS REGISTER and wait
R9[0]?1{      ; if bit0 not READY, error present.
PRINT=A("Chip not respond, continue?")
RA?0{EXIT}
}

[READ]
CS=0

_SEND(00000011b)
LOOP=(15,0){SI=ADR[I],SCK=P}

SI=1

LOOP=(7,0){SCK=1,DATA[I]=SO,SCK=0}

CS=1


[READBLOCK]
CS=0

_SEND(00000011b)
LOOP=(15,0){SI=ADR[I],SCK=P}

SI=1

LOOP=($BLOCKSIZE){
LOOP=(7,0){SCK=1,DATA[I]=SO,SCK=0}
ADR=+1
}

CS=1


[WRITEINIT]
WP=1
CS=1
SCK=0
CS=0
_SEND(00000110b)   ; Write enable
SI=1,CS=1
P=10
CS=0,SI=0
_SEND(00000001b)   ;WRSR 
_SEND(00000000b)   ;Status Register
SI=1,CS=1
P=$WDELAY,P=$WDELAY



[WRITE]
CS=0
_SEND(00000110b)   ; Write enable
CS=1

;HOLD=1
;WP=1
;CS=1
;SCK=0

CS=0
_SEND(00000010b)
LOOP=(15,0){SI=ADR[I],SCK=P}
LOOP=(7,0){SI=DATA[I],SCK=P}
CS=1

P=$WDELAY

[WRITEBLOCK]                                 ; Запись блока  
WP=1
SCK=0
CS=0,SI=0
_SEND(00000110b)   ; Write enable
SI=1,CS=1
P=20
CS=0,SI=0
_SEND(00000010b)   ; Write
LOOP=(15,0){SI=ADR[I],SCK=1,SCK=0}
LOOP=($BLOCKSIZE){LOOP=(7,0){SI=DATA[I],SCK=1,SCK=0},ADR=+1}
SI=1,CS=1
_WAITWR




[ReadStatus]
HOLD=1
WP=0
SCK=0
CS=1
CS=0
_SEND(00000101b)                      	; RDSR
SI=1
LOOP=(7,0){SCK=1,R9[I]=SO,SCK=0}
CS=1
P=10
GET=("Status Register",R9)

[WriteStatus]
GET=("Write Status",R9)
RA?0{EXIT}
HOLD=1
WP=1
SCK=0

CS=0
_SEND(00000110b)   ; Write enable
CS=1
P=20000

CS=0
_SEND(00000001b)                      	; WRSR
_SEND(R9)
CS=1
P=$WDELAY,P=$WDELAY