; Orange programmer module v2.9 ; (c) 2004-2010 CnCLab & pavel-pervomaysk ; SPI EEPROM: ; CHIP=25c010,128x8 25c020,256x8 25c040,512x8 ;Status Register: 7 6 5 4 3 2 1 0 ; (Int. WR Cycle) BP1 BP0 WEN /RDY ; (Only Atmel) ; BP1,BP0 - Block write protect ;GROUP=Atmel ;CHIP=AT25010A,128(8),25040.hpl ;GROUP=ST ;CHIP=M95010WP,128(16),25040.hpl ;CHIP=M95020WP,256(16),25040.hpl ;CHIP=M95040WP,512(16),25040.hpl SOCKET=4 ;"SPI" PINO=SCK,0 PINO=SI,1 PINO=CS,2 PINO=WP,3 PINO=HOLD,4 PINI=SO,1 CDELAY=2 ; one set delay R9=STATUS,C8,7,6,5,4,3,2,1,0 [!#SETUP] $WDELAY=10000 [_SEND] LOOP=(7,0){SI=R0[I],SCK=P} ; Read STATUS register [_RDSR] CS=0 _SEND(00000101b) ;RDSR SI=1 R9=0 LOOP=(7,0){SCK=1,R9[I]=SO,SCK=0} CS=1 ;Wait for end write memory... [_WAITWR] SCK=0 LOOP=(0,1000){ CS=0 _SEND(00000101b) ;RDSR SI=1 R9=0 LOOP=(7,0){SCK=1,R9[I]=SO,SCK=0} CS=1 R9[0]?0{BREAK} ;WIP bit P=20 } [INIT] HOLD=1 WP=0 CS=1 SCK=0 _WAITWR ; READ STATUS REGISTER and wait R9[0]?1{ ; if bit0 not READY, error present. PRINT=A("Chip not respond, continue?") RA?0{EXIT} } [READ] CS=0 SI=0,LOOP=(3,0){SCK=P} ;bits 7-4 = 0 SI=ADR[8],SCK=P ;Hi ADR bits - use only for 25040 R0=011B ;Read Instr. LOOP=(2,0){SI=R0[I],SCK=P} LOOP=(7,0){SI=ADR[I],SCK=P} SI=1 LOOP=(7,0){SCK=1,DATA[I]=SO,SCK=0} CS=1 P=1 [WRITEINIT] WP=1 ; Must held Hi! CS=1 SCK=0 CS=0 _SEND(00000110b) ; WREN - Write enable CS=1 P=20 CS=0 _SEND(00000001b) ;WRSR Instr. _SEND(00000000b) ;Status Register Clear BP bits CS=1 P=$WDELAY [WRITE] SCK=0 CS=0 _SEND(00000110b) ; Write enable CS=1 P=20 CS=0 SI=0,LOOP=(3,0){SCK=P} ;bits 7-4 = 0 SI=ADR[8],SCK=P ;Hi ADR bit - use only for 25040 R0=010B ;Write Instr. LOOP=(2,0){SI=R0[I],SCK=P} LOOP=(7,0){SI=ADR[I],SCK=P} LOOP=(7,0){SI=DATA[I],SCK=P} CS=1 P=$WDELAY [WRITEBLOCK] SCK=0 CS=0 _SEND(00000110b) ; Write enable CS=1 P=20 CS=0 SI=0,LOOP=(3,0){SCK=P} ;bits 7-4 = 0 SI=ADR[8],SCK=P ;Hi ADR bit - use only for 25040 R0=010B ;Write Instr. LOOP=(2,0){SI=R0[I],SCK=P} LOOP=(7,0){SI=ADR[I],SCK=P} LOOP=($BLOCKSIZE){ LOOP=(7,0){SI=DATA[I],SCK=P} ADR=+1 } CS=1 _WAITWR [ReadStatus] SCK=0 CS=1 CS=0 _SEND(00000101b) ; RDSR SI=1 LOOP=(7,0){SCK=1,R9[I]=SO,SCK=0} CS=1 P=10 GET=("Status Register",R9) [WriteStatus] GET=("Status Register",R9) HOLD=1 WP=1 SCK=0 CS=0 _SEND(00000110b) ; Write enable CS=1 P=100 CS=0 _SEND(00000001b) ; WRSR _SEND(R9) CS=1 P=$WDELAY P=$WDELAY