; Orange programmer module V.1.5
; (c) 1999-2003 CnCLab
; CHIP=24LC41,128x8

; 2 - Monitor port
; 24LC41 512+ 128 dual port EEPROM

; primary tested


; Orange1 - not supported.
;Chip   Programmer:
;1 DSCL P3,
;2 DWP  P5,
;3 Vss  Gnd,
;4 MSDA P1,
;5 MSCL P0
;6 MWP  P2,
;7 VCC  Vcc
;8 DSDA P4,

SOCKET=0 ; 
INFO="24LC41 Adapter" 
ALLPINS=8
 

PING=MSCL,0,5
PING=MSDA,1,4
PINO=MWP, 2,6
PING=DSCL,3,1
PING=DSDA,4,8
PINO=DWP, 5,2

CDELAY=4                              ; one cycle time

[_START]
DSDA=1,DSCL=1,DSDA=0,DSCL=0               ; Start  10

[_STOP]
DSCL=0,DSDA=0,DSCL=1,DSDA=1               ; Stop   01

[_PWAIT]        ; polling wait
R0=0
R1=0xA0
LOOP=(0,60){
_START
LOOP=(7,0) {DSDA=R1[I],DSCL=1,DSCL=0} ; out 8 bits
DSDA=1,DSCL=1,R0[0]=DSDA              ; ack store
DSCL=0,DSDA=0
_STOP
R0?0{BREAK} 
P=500
}



[INIT]
MWP=0
; switch to BI-DIRECTIONAL MODE
DSDA=1
LOOP=(7,0){DSCL=0,DSCL=1}



[READ]
_START
R0=0xA
LOOP=(3,0) {DSDA=R0[I],DSCL=1,DSCL=0}   ; out 4 bits DeviceAdr
LOOP=(10,8){DSDA=ADR[I],DSCL=1,DSCL=0}   ; out 3 bits Hi(Adr)
DSDA=0,DSCL=1,DSCL=0                     ; out 1 bit, 0=Write Mode
DSDA=1,DSCL=1,DSDA?0,DSCL=0               ; ACKN check
                                      ; end  out  DeviceAdr, Hi(Adr), Mode

LOOP=(7,0) {DSDA=ADR[I],DSCL=1,DSCL=0}   ; out 8 bits Lo(Adr)
DSDA=1,DSCL=1,DSDA?0,DSCL=0               ; ACKN check
                                      ; end  out   Lo(Adr)

_START
R0=0xA
LOOP=(3,0) {DSDA=R0[I],DSCL=1,DSCL=0}    ; out 4 bits DeviceAdr
LOOP=(10,8) {DSDA=ADR[I],DSCL=1,DSCL=0}  ; out 3 bits Hi(Adr)
DSDA=1,DSCL=1,DSCL=0                     ; out 1 bit, 1=Read Mode
DSDA=1,DSCL=1,DSDA?0,DSCL=0               ; ACKN  check
                                      ; end  out  DeviceSelect

LOOP=(7,0) {DSCL=1,DATA[I]=DSDA,DSCL=0}  ; read byte Data
DSDA=1,DSCL=1,DSCL=0                     ; out  master  NO_ACKN

_STOP


[WRITE]
_START
R0=0xA
LOOP=(3,0) {DSDA=R0[I],DSCL=1,DSCL=0}    ; out 4 bits DeviceAdr
LOOP=(10,8) {DSDA=ADR[I],DSCL=1,DSCL=0}  ; out 3 bits Hi(Adr)
DSDA=0,DSCL=1,DSCL=0                     ; out 1 bit, 0=Write Mode
DSDA=1,DSCL=1,DSDA?0,DSCL=0               ; ACKN check
                                      ; end  out DeviceAdr, Hi(Adr), Mode

LOOP=(7,0) {DSDA=ADR[I],DSCL=1,DSCL=0}   ; out 8 bits Lo(Adr)
DSDA=1,DSCL=1,DSDA?0,DSCL=0               ; ACKN check
                                      ; end  out   Lo(Adr)

LOOP=(7,0) {DSDA=DATA[I],DSCL=1,DSCL=0}  ; out byte Data
DSDA=1,DSCL=1,DSDA?0,DSCL=0               ; ACKN  check
                                          ; end out Data
_STOP

P=10000                               ; delay: (Write Time)
;_PWAIT